1. Field of the Invention
The present invention relates to non-volatile memory.
2. Description of the Related Art
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage (VTH) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory element can be programmed/erased between two states, e.g., an erased state and a programmed state. Typically, memory cells having a threshold voltage within a first voltage range are considered to be in the erased state and those having a threshold voltage within a second voltage range are considered to be in the programmed state. Typically, there is a window between the first and second range. Such a flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one bit of data.
A multi-state (also called multi-level) flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, each memory element can store two bits of data when the element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges.
Some flash memory devices operate as both binary and multi-states. For example, some memory cells are used to store one bit of data (“single-level cell or SLC blocks”) and other memory cells are used to store multiple bits per cell (“multi-level cell or MLC blocks”). For some devices, the SLC blocks and MLC blocks are part of the same integrated circuit, and may even be part of the same memory array. The SLC blocks may be used for short term storage of data, whereas the MLC blocks may be used for long term data storage. In other words, the SLC blocks might be used somewhat like a cache. Thus, the SLC blocks may be programmed/erased many more times over the life of the device than MLC blocks. Therefore, write/erase endurance may be a more significant problem for SLC blocks than for MLC blocks.
For some memory arrays, the array is arranged as a number of parallel word lines and a number of bit lines that run perpendicular to the word lines. Each memory cell may be associated with one word line and one bit line. In certain situations, a memory cell can be affected by the charge stored on the floating gate of an adjacent memory cell on a neighboring word line and/or neighboring bit line.
Shifts in the apparent charge stored on a floating gate of a memory cell can occur because of the coupling of an electric field due to the charge stored in adjacent floating gates. This phenomenon is described in U.S. Pat. No. 5,867,429, which is incorporated herein by reference in its entirety. The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. For example, a first memory cell is programmed to add a level of charge to its floating gate that corresponds to one set of data. Subsequently, one or more adjacent memory cells are programmed to add a level of charge to their floating gates that correspond to a second set of data. After the one or more of the adjacent memory cells are programmed, the charge level read from the first memory cell appears to be different than programmed because of the effect of the charge on the adjacent memory cells being coupled to the first memory cell. The coupling from adjacent memory cells can shift the apparent charge level being read a sufficient amount to lead to an erroneous reading of the data stored. Herein, this adjacent floating gate to floating gate effect may be referred to as one type of “adjacent floating gate charge coupling effect.”
The charge on an adjacent floating gate can also interfere with the conductive channel in the substrate below the floating gate of a memory cell. Specifically, the charge on the adjacent floating gate may impact how strongly the channel of another memory cell conducts a current. Thus, if the charge stored in an adjacent floating gate changes, then it may require a greater (or smaller) voltage on the control gate the other memory cell to create the same current in the channel. The net impact is that the amount of charge stored on the memory cell appears to be different due to the change in the charge stored in the adjacent floating gate. This problem is most pronounced between sets of adjacent memory cells that have been programmed at different times. Herein, this adjacent floating gate to channel effect may be referred to as another type of “adjacent floating gate charge coupling effect.”
Another problem with memory cells is that over time charge can accumulate in a dielectric near the floating gate. For example, when programming a memory cell, charge can become trapped in a tunnel oxide layer below the floating gate of the memory cell. Erasing the memory cell may not completely remove the trapped charge. With each program/erase cycle, the amount of trapped charge increases.
As memory cells continue to shrink in size, the associated reduction in space between memory cells may increase the adjacent floating gate charge coupling effects. As the number of program/erase cycles increases, the charge trapping around adjacent floating gates exacerbates the floating gate charge coupling effects. For memory cells which undergo many program/erase cycles, the large adjacent floating gate charge coupling effects severely shrinks the difference between the threshold voltage ranges. For example, the gap between the range of threshold voltages that represents a “1” and “0” decreases. To guarantee reliability and avoid read errors, there should be a certain amount of threshold voltage separation between the “1” state and the “0” state.